`timescale 1ns/100ps

module project3_multiplier_testbench();

wire oDone;
wire [15:0]oProduct;
reg iClk, iReset, iReady;
reg [7:0] iMultiplier, iMultiplicand;

project3_multiplier p3m00(iClk,iReset,iReady,oDone,iMultiplier,iMultiplicand,oProduct);

always begin
#1 iClk=~iClk;
end

initial begin
#0 iClk<=0; iReset<=1; iReady<=0; iMultiplier=8'b00000000; iMultiplicand=8'b00000000;
#20 iReset<=0; iReady<=0; iMultiplier=8'b01011011; iMultiplicand=8'b00010010;
#20 iReset<=0; iReady<=1; iMultiplier=8'b01011011; iMultiplicand=8'b00010010;
#20 iReset<=1; iReady<=0; iMultiplier=8'b00000000; iMultiplicand=8'b00000000;
#20 iReset<=0; iReady<=0; iMultiplier=8'b10011101; iMultiplicand=8'b00000111;
#20 iReset<=0; iReady<=1; iMultiplier=8'b10011101; iMultiplicand=8'b00000111;
#20 iReset<=1; iReady<=0; iMultiplier=8'b00000000; iMultiplicand=8'b00000000;
#20 iReset<=0; iReady<=0; iMultiplier=8'b01011011; iMultiplicand=8'b00010010;
#20 iReset<=0; iReady<=1; iMultiplier=8'b01011011; iMultiplicand=8'b00010010;
#10 iReset<=1; iReady<=0; iMultiplier=8'b00000000; iMultiplicand=8'b00000000;
end

endmodule
